Responsibilities

  • Responsible for Development of New Product Line and Yield/Quality Improvement
  • Understanding system/customer requirement and optimization of the products to meet requirement.
  • Characterization of the Read Window Budget (RWB), performance, and reliability of the product;
  • Support design verification and in-depth circuit analysis of new products using CAD tools and Verilog simulations
  • Perform electrical failure analysis to understand the root cause of the product issue
  • Work with the wafer fab process/integration group to address process-related defects affecting product yield
  • Identify design marginalities and recommend design fix for circuit-related problems
  • Utilize state-of-the-art high-speed equipment to support product characterization and electrical failure analysis
  • Ability to perform in-depth RWB (Read Window Budget) analysis and propose and implement trim changes to meet requirement.
  • Define algorithms to be implemented in our production test flows to better optimize RWB, performance, reliability, and yield at a die-level, and to reduce variation across the manufacturing line;
  • Participate in cross-functional efforts to document, standardize, and improve our capability to optimize RWB on future products.

Requirements

  • Bachelor's/Master's Degree in Electrical/Electronics Engineering
  • Good understanding of CMOS device physics
  • Knowledge of CMOS circuit design and CAD/Simulation is an added advantage
  • Effective communication skills in written and spoken English
  • Excellent problem solving skills and strong presentation skill
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