Job Description

The main areas of responsibility would be one or more of the following:

  • SoC DFT architecture specification including test muxing and DfT RTL coding.
  • IEEE1149.1 Boundary Scan design.
  • Scan Insertion, ATPG, scan verification and pattern generation.
  • Memory BIST insertion, validation and pattern generation.
  • Functional Pattern generation.
  • Pattern debug on ATE.
  • Design Verification for DFT.
  • ATE correlation activities on bench validation environment.

Qualifications

  • Bachelors in Engineering.
  • Exposure to digital IC design techniques, flows and methodologies including, but not limited to:
    • RTL coding, Design verification.
    • Design for Test, Synthesis.
  • Prior knowledge of IC design tools:
    • Cadence NCSIM
    • Synopsys VCS
    • Mentor Tessent Shell

Inside this Business Group

Communication & Devices Group: The wireless revolution at Intel! We are one team - passionate engineers and technologists from diverse industry backgrounds working together to realize a world of connected computing. We are bringing the best ideas from the brightest minds to deliver future mobile experiences into the market. We are on the journey towards making Intel a wireless leader with exciting products for the Internet of Things, 5G and an opportunity to change the world with your work.

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